The present invention relates to current-fed twelve-step current wave inverters or twelve-step current source inverters.
A current source inverter of a multiple-step type is known in the art in which, as shown in FIG. 1, inverters INV1 and INV2 are connected in parallel with a common DC source 11 through DC reactors 12 to 15 which smooth the DC current supplied from the DC source 11. The first inverter INV1 forms a first three-phase bridge with positive-terminal-side first main valves UP1, VP1 and WP1 with control gate and negative-terminal-side second main valves UN1, VN1 and WN1 with control gate. The second inverter INV2 forms a second three-phase bridge with positive-terminal-side first main valves UP2, VP2 and WP2 with control gate and negative-terminal-side second main valves UN2, VN2 and WN2 with control gate. Although not shown, each of the first and second inverters includes first and second commutating devices for quenching the first and second main valves. Usually, the main valves are each comprised of a thyristor, and numeral 16 designates for example an AC motor which receives the resultant output currents of the inverters INV1 and INV2. To increase the capacity of the twelve-step current source inverter and also to improve its output waveform, the DC input voltages applied to the first and second inverters INV1 and INV2 must be made equal to each other. A control unit 410 applies to the control gates of the main valves those pulses which determine the firing order and firing intervals of the main valves in the first and second inverters INV1 and INV2.
It is well known in the art that the desired reduction of the lower order harmonics in the resultant output currents of a twelve-step current source inverter can be achieved by the phase-shifted addition of two inverter output currents resulting in a twelve-step load line current.
Known systems of the above type are shown, as for example, in Japanese Patent Application No. 15863/76, which was published before examination as Laying-open No. 52-100124, entitled "Control System for Multiple-Step Current Source Inverters".
The resultant output currents of this type of twelve-step current source inverter have the waveforms as shown in FIG. 2. In FIG. 2(a), I.sub.p1 represents the direct current flowing to the positive-side main valves of the first inverter INV1. I.sub.P2 indicates the direct current flowing to the positive-side main valves of the second inverter INV2. I.sub.N1 indicates the direct current flowing to the negative-side main valves of the first inverter INV1. I.sub.N2 indicates the direct current flowing to any one of the negative-side main valves of the second inverter INV2.
Shown in FIG. 2(b) is a U-phase output current IU. Shown in FIG. 2(c) is a timing of control gate pulses applied to the control gates of the positive-side first main valves UP1, VP1 and WP1 of the first inverter INV1. Shown in FIG. 2(d) is a timing of control gate pulses applied to the control gates of the positive-side first main valves UP2, VP2 and WP2 of the second inverter INV2. Shown in FIG. 2(e) is a timing of control gate pulses applied to the control gates of the negative-side second main valves UN1, VN1 and WN1 of the first inverter INV1. Shown in FIG. 2(f) is a timing of control gate pulses applied to the negative-side second main valves UN2, VN2 and WN2 of the second inverter INV2. These gate pulses are produced by the control unit 410 with respective pulse widths of predetermined time intervals and applied sequentially to the control gates of the positive-side first main valves and the negative-side second main valves of the first and second inverters INV1 and INV2 in the order of the 1st phase (U phase), 2 nd phase (V phase) and 3rd phase (W phase). In this case, as shown in FIG. 2, the waveforms of the direct currents I.sub.P1 and I.sub.P2 and that of the output current IU are distorted as compared with that of an ideal rectangular wave for the following reasons. In other words, as will be seen from FIGS. 2(c) and 2(d), the main valves UP1 and WP2 are turned on during the time interval between times t.sub.0 and t.sub.1 and consequently the AC line voltage between the lines U and W of the motor 16 is applied to the series connection of the DC reactors 12 and 13. This causes the currents flowing to the DC reactors 12 and 13 to change. Thus, in the case of the current I.sub.P1 flowing to the main valve UP1, for example, it varies as shown by the i-to-j portion in FIG. 2(a). During the next time period t.sub.1 to t.sub.4, the main valves UP1 and UP2 are turned on so that the terminal voltage of the motor 16 is not applied to the DC reactors 12 and 13 and the fixed current from the DC source 11 flows to zhe DC reactors 12 and 13. Thus, in the case of the current I.sub.P1, for example, it varies as shown by the j-to-k portion in (a) of FIG. 2. During the next time period t.sub.4 to t.sub.5, the main valves UP1 and VP2 are turned on and consequently the AC line voltage between the lines U and V of the motor 16 is applied to the DC reactors 12 and 13. In this case, due to the following reasons, the polarity of the DC current flowing through a series circuit of the reactors 12 and 13 during the time period t.sub.4 to t.sub.5 is opposite to the polarity of such DC current flowing during the time period t.sub.0 to t.sub.1 and the current I.sub.P1 varies as shown by the k-to-l portion in FIG. 2(a). Namely, since the main valve UP1 is fired prior to the main valve UP2 during the time period t.sub.0 to t.sub.1 as will be seen from FIGS. 2(c) and 2(d), the voltage applied to the DC reactors 12 and 13 is in a direction from the reactor 12 toward the reactor 13. On the contrary, during the time period t.sub.4 to t.sub.5 the main valve VP2 is fired before the main valve VP1 as will be seen from FIGS. 2(c) and 2(d) and consequently the voltage applied to the DC reactors 12 and 13 is in a direction from the latter toward the former. As a result, the current I.sub.P1 flowing to the main valve UP1 varies during the period t.sub.0 to t.sub.1 in a direction opposite to the direction in variation of the same during the period t.sub.4 to t.sub.5. On the other hand, as shown in FIG. 2(a), the current I.sub.p2 flowing to the main valve UP2 presents a waveform varying oppositely in direction to the current I.sub.P1 due to the change of direction of the voltage applied to the DC reactors 12 and 13. The same operation is performed repeatedly and consequently the currents I.sub.P1, I.sub.P2, I.sub.N1 and I.sub.N2 flowing to the main valves result in pulsating waveforms as shown in FIG. 2(a). Consequently, the resulting output current waveform IU results in a waveform as shown in FIG. 2(b). In other words, since the main valve UP1 is fired prior to the main valve UP2 during the period t.sub.0 to t.sub.1, during this period, as shown at i' to j', the i-to-j component of the current flowing to the main valve UP1 appears as such in the IU phase as the U-phase output current IU. During the period t.sub.1 to t.sub.4 the currents I.sub.P1 and I.sub.P2 flowing to the main valves UP1 and UP2 during the period are superposed one upon another and result in the U-phase output current IU as shown by the j"-to-k" portion. In the like manner, the U-phase output current IU appears as shown by the k'-to-l' portion during the period t.sub.4 to t.sub.5. Thus the waveform of the U-phase output current IU becomes as shown in FIG. 2(b).
In the twelve-step current source inverter shown in FIG. 1 the DC source 11 is provided in common to serve for the first and second inverters INV1 and INV2. As a result, the current flowing to the first and second inverters INV1 and INV2, respectively, cannot be controlled separately and the total value of the currents flowing from the DC source 11 to the first and second inverters INV1 and INV2 is controlled by for example a rectifier comprising a thyristor. When the twelve-step current source inverter is functioning normally, the average value of the current flowing to the first inverter INV1 becomes equal to that of the second inverter INV2. However, when any irregularity occurs, that is, when a commutation failure occurs in the first inverter INV1, the DC current flowing to the first inverter INV1 becomes unequal to that of the second inverter INV2. In such a case, it is necessary to detect rapidly the occurrence of an irregularity in the balance between the currents in the first and second inverters INV1 and INV2.
FIG. 3 shows an inverter of the above-described type which incorporates a fault detecting circuit for such purposes. In the Figure, numerals 17, 18, 19 and 20 designate current transformers disposed to respectively detect the DC current passed through DC reactors 12, 13, 14 and 15, respectively. The same reference numerals as used in FIG. 1 designate the identical or equivalent components. Since it is practically difficult to reduce the ripple factor of direct current to less than 30% for economical reasons, the resulting direct current detection signals must be smoothed by filters 21, 22, 24 and 25. The direct current detection signals passed through the filters 21, 22 and 24, 25, respectively, are applied to comparators 23 and 26 adapted to respectively detect that the difference between the currents I.sub.P1 and I.sub.P2 flowing to the main valves UP1 and UP2 as shown in FIG. 2(a) has exceeded a maximum deviation value z and a fault detection signal 27 or 28 is generated when the maximum deviation value z is exceeded. Numeral 500 designates combining means for combining the first and second inverters of currents to derive a three-phase system of resultant output currents.
The fault detecting circuit shown in FIG. 3 has a serious disadvantage that the use of the filters 21, 22, 24 and 25 causes a time delay in the detection of an abnormal current, thus tending to damage the main valves each comprising a thyristor or the like.